Patel, Maharshi; Parmar, Yogesh; Suthar, Haresh
(International Journal of Innovative Technology and Exploring Engineering (IJITEE) | Volume-9 | Issue-5, 2020-03)
Test time reduction is a prominent challenge in scan based Design For Testability (DFT) architectures for cost effective test. Reliability and testability both are main objectives for DFT in today’s VLSI design. In this ...