http://localhost:8080/xmlui/handle/123456789/7161 Sun, 12 Apr 2026 01:57:01 GMT 2026-04-12T01:57:01Z http://localhost:8080/xmlui/handle/123456789/7207 Reduction of test timeduring design for testability Patel, Maharshi As VLSI technology is continuously shrinking to lower technology nodes we need efficient technique for testing. Now, reliability and testability both are the important parameters in today’s VLSI design. Reducing the testing time is major challenge in scan based DFT (or test) the sequence that, when applied to a digital circuit, it will enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. Now, ATE machines are very expensive machine i.e. (i) more number of test patterns will take more time to execute and that result in more cost. (ii) more data architecture for cost-effective test. So, more pattern volume will require more storage capacity. Larger pattern volume need more time for scan operation in DUT also. DFT Compiler from Synopsys is used to generate the verified scan design. ATPG tool generate vectors that can detect volume needed more memory to store, that will result in more cost. The ATPG tool generates a statistics report later that tells us what the tool has done and provides fault category information that we have to interpret to debug coverage problems. Test-time improvement by reordering the scan cells as per priority is the main focus of this dissertation. I achieved significant DFT-debugging time of 19.56% with compare to normal scan operation by adding STCPI and reordering the scan chains. For Full Thesis Kindly contact to respective Library Wed, 01 May 2019 00:00:00 GMT http://localhost:8080/xmlui/handle/123456789/7207 2019-05-01T00:00:00Z http://localhost:8080/xmlui/handle/123456789/7168 Face detection for student attendance using deep learning Shah, Milan This Face detection is the task of identifying an individual student’s face and their database recognized deep learning. Face detection is largest technology with attendance of students.The system uses viola Jones algorithm in facial features. The student’s features compare to faces between system managers them efficient. The features allow to compare faces between system manager them efficient. Used SVM(support vector machine).The student’s faces detection local binary pattern and Recognition and facing detection method codes used sequentially. This project statistical approach using data objects which included method analysis. For Full Thesis Kindly contact to respective Library Mon, 01 Apr 2019 00:00:00 GMT http://localhost:8080/xmlui/handle/123456789/7168 2019-04-01T00:00:00Z http://localhost:8080/xmlui/handle/123456789/7166 Enhancement of night time video using dark channel prior ip accelerator Nambinina, Rakotojaona Enhancement of night-time video using Dark Channel Prior IP accelerator is proposed in this thesis. Nighttime video processing is difficult due to low brightness, low contrast and high noise in the video. The above problems may affect the accuracy and may results in failures of object detection or object classification at night time. Dark Channel Prior (DCP) filter is used to improve the visibility, brightness, and contrast of the night-time input video. Processing speed is a challenging task on the real-time application of the DCP algorithm for night time video enhancement. Hence, the DCP algorithm is implemented on FPGA (ALVEO Board) to increase the speed of video processing. In order to demonstrate the quality of the proposed method, a practical environment with a Vitis software tool and Alveo board was also set up to evaluate the performance of hardware. Such extensive experimental results indicate that the proposed algorithm and hardware structure are effective, feasible and straightforward to apply to practice. For Full Thesis Kindly contact to respective Library Wed, 01 Apr 2020 00:00:00 GMT http://localhost:8080/xmlui/handle/123456789/7166 2020-04-01T00:00:00Z http://localhost:8080/xmlui/handle/123456789/7165 Amba based ahb2apb bridge rtl design in verilog and verification in system verilog Panchal, Bhagvati The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for high performance buses to communicate with low-power devices. The AMBA AHB is for high-performance, high clock frequency system modules. In the AMBA Advanced High Performance bus (AHB) is used to connect a processor, a DSP, and high-performance memory controllers. The AMBA APB is optimized for low power consumption and interface reduced complexity to support peripheral functions. It also contains a Bridge, which connects the AHB and APB buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented using VERILOG tool and tested using Verilog testbench by simulating it in XILINX ISE. Also, we verify the all functions and specification of Bridge protocol by writing verification code using Universal Verification Methodology(UVM). The code coverage and functional coverage and functional verification of the Bridge RTL design will get 100 percent covered by QUESTASIM. For Full Thesis Kindly contact to respective Library Wed, 01 Apr 2020 00:00:00 GMT http://localhost:8080/xmlui/handle/123456789/7165 2020-04-01T00:00:00Z