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Browsing by Author "Patel, Maharshi"

Browsing by Author "Patel, Maharshi"

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  • Reduction of Test Time using Multiple Test Control Point Insertion for 7nm Technology Node 
    Patel, Maharshi; Parmar, Yogesh; Suthar, Haresh (International Journal of Innovative Technology and Exploring Engineering (IJITEE) | Volume-9 | Issue-5, 2020-03)
    Test time reduction is a prominent challenge in scan based Design For Testability (DFT) architectures for cost effective test. Reliability and testability both are main objectives for DFT in today’s VLSI design. In this ...
  • Reduction of test timeduring design for testability 
    Patel, Maharshi (Parul University, 2019-05-01)
    As VLSI technology is continuously shrinking to lower technology nodes we need efficient technique for testing. Now, reliability and testability both are the important parameters in today’s VLSI design. Reducing the testing ...